Algorithms and VLSI Architectures for Low-Power Mobile Face Verification

Among the biometric modalities suitable for mobile applications, face verification is definitely an interesting one, because of its low level of invasiveness, and because it is easily applicable from the user viewpoint. Additionally, a reduced cost of the identity verification device is possible when sharing the imaging device between different applications. This is for instance not possible with fingerprint verification, which asks for a specific sensor. This Ph.D. thesis addresses the problem of conceiving a low-power face authentication system adapted to the stringent requirements of mobile communicators, including the study and design of the algorithms, and the mixed hardware and software implementation on a dedicated multi-processors platform. With respect to the anterior state-of-art, this thesis proposes several original algorithmic improvements, and an original architecture for a VLSI System-On-Chip realization, where the algorithmic and architectural aspects have been jointly optimized, so as to enable the execution of the face verification to be entirely processed on low-power mobile devices such as mobile phones, or personal digital assistants. At the time when this work was undertaken and completed, there were no similar results published either from the academic scientific community, or from the market in form of a product description / announcement. The mobile environment is known to be characterized by large variations in image acquisition conditions with regard to the scene acquisition viewpoint and illumination, and it is therefore requiring a sound optimization of the algorithmic robustness. Moreover, face verification is a quite complex task that is usually performed on powerful possibly